Power-Up Sequencing
The timing requirements for processor startup are given in
Note that during power-up, a leakage current of approximately
200 μA may be observed on the RESET pin. This leakage current
results from the weak internal pull-up resistor on this pin being
enabled during power-up.
Table 13. Power Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
t RSTVDD
RESET Low Before V DDINT /V DDEXT On
0
ns
t IVDDEVDD
V DDINT on Before V DDEXT
–50
+200
ms
t CLKVDD
t CLKRST
t PLLRST
1
CLKIN Valid After V DDINT /V DDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
0
10 2
20 3
200
ms
μs
μs
Switching Characteristic
t CORERST
Core Reset Deasserted After RESET Deasserted
4096 × t CK + 2 × t CCLK 4, 5
1
2
3
4
5
Valid V DDINT /V DDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume
a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
The 4096 cycle count depends on t SRST specification in Table 15 . If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
RESET
V DDINT
V DDEXT
t RSTVDD
t IVDDEVDD
t CLKVDD
CLKIN
t CLKRST
CLK_CFG1–0
RESETOUT
t PLLRST
Figure 5. Power-Up Sequencing
Rev. D | Page 20 of 56 | April 2013
t CORERST
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